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Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the techno...
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Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35 /spl mu/m to 0.07 /spl mu/m projected in the National Technology Roadmap for Semiconductors.
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Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability...
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Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability (Silveira et al., 1996). Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. We address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm (Ruhe, 1994). The scheme reduces to that of (Odabasioglu et al., 1997) when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced order models.
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This article proposes an efficient algorithm by module duplication for integration of high-level synthesis and floorplan to optimize the interconnect delay and power. Module duplication can bring down the interconnect wire length ...
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This article proposes an efficient algorithm by module duplication for integration of high-level synthesis and floorplan to optimize the interconnect delay and power. Module duplication can bring down the interconnect wire length among physical modules, thereby further reducing the interconnect delay and power. With the proper generosity of the area constraint, incremental high-level synthesis and floorplan procedures are proposed to perform iteratively for finding the best place for the duplicated module to be inserted. The key contribution of the algorithm lies in the fact that our designs are 20.8% more interconnect delay-efficient and 12.5% more interconnect power-efficient over the results produced by original design methods
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摘要 :
This article proposes an efficient algorithm by module duplication for integration of high-level synthesis and floorplan to optimize the interconnect delay and power. Module duplication can bring down the interconnect wire length ...
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This article proposes an efficient algorithm by module duplication for integration of high-level synthesis and floorplan to optimize the interconnect delay and power. Module duplication can bring down the interconnect wire length among physical modules, thereby further reducing the interconnect delay and power. With the proper generosity of the area constraint, incremental high-level synthesis and floorplan procedures are proposed to perform iteratively for finding the best place for the duplicated module to be inserted. The key contribution of the algorithm lies in the fact that our designs are 20.8% more interconnect delay-efficient and 12.5% more interconnect power-efficient over the results produced by original design methods
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The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled...
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The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.
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摘要 :
The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled...
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The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.
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Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the comple...
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Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.
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Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the comple...
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Double patterning lithography is an important solution for critical layers with sub-64nm pitch interconnects. The overlay created by double patterning technology could add an extra capacitance variation, which increases the complexity of parasitic capacitance extractions. In this study, we mainly analyzed the effect of double patterning overlay on the intra-layer capacitance, inter-layer capacitance and process corner.
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Reliable interconnection with low resistance is substantially required on DRAM with 90 nm design rule in terms of its integration and functionality. Several key interconnect technologies, including poly metal gate, W bitline, cont...
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Reliable interconnection with low resistance is substantially required on DRAM with 90 nm design rule in terms of its integration and functionality. Several key interconnect technologies, including poly metal gate, W bitline, contact and via processes using advanced CVD-Al, are described. Full metal interconnected DRAM exhibits excellent performance and even further scalability.
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摘要 :
Reliable interconnection with low resistance is substantially required on DRAM with 90 nm design rule in terms of its integration and functionality. Several key interconnect technologies, including poly metal gate, W bitline, cont...
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Reliable interconnection with low resistance is substantially required on DRAM with 90 nm design rule in terms of its integration and functionality. Several key interconnect technologies, including poly metal gate, W bitline, contact and via processes using advanced CVD-Al, are described. Full metal interconnected DRAM exhibits excellent performance and even further scalability.
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